ESD Protection Design Using Copper Interconnects: More Robustness And Less Parasitics

This report presents a comprehensive investigation on the advantages of using copper interconnects in ESD protection designs. 4KV GGMOS ESD protection structures using Cu interconnects, a 2GHz ring oscillator circuit and a low-power, high-speed Op Amp circuit were designed for comparison study. In Phase I, simulation results show that, while ESD protection devices may inevitably affect circuit operation, the use of Cu interconnects can not only significantly improve the ESD robustness (> +30%) but also substantially reduce the unavoidable negative influences (~ +20%) of the ESD protection devices on the core IC chips protected. In Phase II, the simulation findings were partially confirmed by measurement data. Testing results for individual Cu ESD metal test structures match the simulation reasonably well, which proved that Cu indeed provides superior ESD performance compared with Al. It also confirmed that, using ESD simulation, much less ESD metal coverage is actually needed to assure same ESD protection than that suggested by traditional ESD metal design rules. Alternatively, these findings suggest that substantially less ESD-induced parasitic effects on overall circuit performance may be expected in Cu technology compared with its Al counterpart for adequate ESD protection. This work clearly demonstrates the benefits of using Cu interconnects in high-speed designs to realize both higher ESD robustness and lower ESD-related parasitic effects as compared to the traditional Al interconnects. Unfortunately, the latter argument cannot be confirmed in measurements because our circuits do not function properly due to missing N+ layers.